集成电路设计中心 企业学院 曙海集团嵌入式学院 就业培训基地长期班 研发与生产

 
嵌入式培训
嵌入式Linux就业班马上开课了 详情点击这儿
上海:021-51875830
北京:010-51292078
深圳:4008699035
南京:4008699035
武汉:027-50767718
成都:4008699035
广州:4008699035
西安:029-86699670
石家庄:4008699035
曙海全国统一报名免费电话
曙海研发与生产请参见网址:
www.shanghai66.cn
全英文授课课程(Training in English)
  首 页  手机阅读模式  课程介绍 培训报名  企业培训   付款方式   讲师介绍  学员评价  关于我们   联系我们   承接项目 开发板商城   就业
嵌入式协处理器--FPGA
FPGA项目实战系列课程----
嵌入式OS--4G手机操作系统
嵌入式协处理器--DSP
手机/网络/动漫游戏开发
嵌入式OS-Linux
嵌入式CPU--ARM
嵌入式OS--WinCE
单片机培训
嵌入式硬件设计
Altium Designer Layout高速硬件设计
嵌入式OS--VxWorks
PowerPC嵌入式系统/编译器优化
PLC编程/变频器/数控/人机界面 
开发语言/数据库/软硬件测试
3G手机软件测试、硬件测试
芯片设计/大规模集成电路VLSI
云计算、物联网
开源操作系统Tiny OS开发
小型机系统管理
其他类
WEB在线客服
南京WEB在线客服
武汉WEB在线客服
西安WEB在线客服
广州WEB在线客服
点击这里给我发消息  
QQ客服一
点击这里给我发消息  
QQ客服二
点击这里给我发消息
QQ客服三
公益培训通知与资料下载
企业招聘与人才推荐(免费)

合作企业最新人才需求公告

◆招人、应聘、人才合作,
请把需求发到officeoffice@126.com或
访问曙海旗下网站---
电子人才网
www.morning-sea.com.cn
合作伙伴与授权机构
现代化的多媒体教室
曙海招聘启示
邮件列表
 
 
  Synopsys SystemVerilog验证培训
   班级规模及环境--热线:4008699035 手机:15921673576( 微信同号)
       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。
   师资团队
赵老师

大规模集成电路设计专家,10多年超大规模电路SOC芯片设计和版图设计经验,参与过DSP、GPU、DTV、WIFI、手机芯片、物联网芯片等芯片的研发。精通CMOS工艺流程、版图设计和布局布线,精通SOC芯片 设计和版图设计的各种EDA工具(如:DC/Prime Time/Encounter/Virtuoso/Calibre/Dracula/Assura),具有丰富的SOC芯片设计、验证、DFT、PD、流片经验。
熟练掌握版图设计规则并进行验证及修改;熟练掌握Unix/Linux操作系统;熟悉CMOS设计规则、物理设计以及芯片的生产流程与封装。

王老师

资深IC工程师,十几年集成电路IC设计经验,精通chip的规划、数字layout、analog layout和特殊电路layout。先后主持和参与了近三百颗CHIP的设计与版图Layout工作,含MCU芯片、DSP芯片、LED芯片、视频芯片、GPU芯片、通信芯片、LCD芯片、网络芯片、手机芯片等等。
从事过DAC、ADC、RF、OP、PLL、PLA、LNA、ESD、ROM、RAM等多种制程analog&digital的电路IC设计,
熟练掌握1.8V,3.3V,5V,18V,25V,40V等各种高低压混合电路的IC设计。

张老师

从事数字集成电路设计10余年,精通CMOS工艺流程、版图设计和布局布线,精通VERILOG,VHDL语言,
擅长芯片前端、后端设计和复杂项目实施的规划管理,其领导开发的芯片已成功应用于数个国际知名芯片厂商之产品中。丰富的芯片开发经验,对于现今主流工艺下的同步数字芯片设计技术和流程有良好把握。长期专注于内存控制器等产品的研发,拥有数颗规模超过百万门的数字芯片成功流片经验.

更多师资力量请见曙海师资团队
   教学优势

  曙海教育的数字集成电路设计课程培养了大批受企业欢迎的工程师。大批企业和曙海
建立了良好的合作关系。曙海教育的数字集成电路设计课程在业内有着响亮的知名度。

  本课程,秉承12年积累的教学品质,以IC项目实现为导向,老师将会与您分享数字芯片设计的全流程以及Synopsy和Cadence公司EDA工具的综合使用经验、技巧。

  本课程,以实战贯穿始终,让您绝对受益匪浅!

远程培训
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山学院/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦
最近开课时间(周末班/连续班/晚班)
Synopsys SystemVerilog验证培训:C语言培训班:2019年12月16日
   实验设备
     ◆课时: 一个月

        
        ☆注重质量
        ☆边讲边练

        ☆合格学员免费推荐工作

        ☆合格学员免费颁发相关工程师等资格证书,提升您的职业资质

        专注高端培训15年,曙海提供的证书得到本行业的广泛认可,学员的能力
        得到大家的认同,受到用人单位的广泛赞誉。

        ★实验设备请点击这儿查看★
   最新优惠
       ◆在读学生凭学生证,可优惠500元。
   质量保障

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、培训结束后免费提供半年的技术支持,充分保证培训后出效果;
        3、培训合格学员可享受免费推荐就业机会。

  Synopsys SystemVerilog验证培训
培训方式以讲课和实验穿插进行

课程描述:

第一阶段 SystemVerilog Assertions培训

COURSE OUTLINE
* Introduction to assertions
* SVA checker library
* Use Model and debug flow using DVE
* Basic SVA constructs
* Temporal behavior, Data Consistency
* Coverage, Coding Guidelines

第二阶段 SystemVerilog Testbench

Overview

In this intensive, three-day course, you will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS.

This course is a hands-on workshop that reinforces the verification concepts taught in lecture through a series of labs. At the end of this class, students should have the skills required to write an object-oriented SystemVerilog testbench to verify a device under test with coverage-driven constrained-random stimulus using VCS.

Students will first learn how to develop an interface between the SystemVerilog test program and the Device Under Test (DUT). Next the workshop will explain how the intuitive object-oriented technology in SystemVerilog testbench can simplify verification problems. Randomization of data is covered to show how different scenarios for testing may be created. This course concludes with an in-depth discussion of functional coverage including a uniform, measurable definition of functionality and the SystemVerilog constructs that allow you to assess the percentage of functionality covered, both dynamically and through the use of generated reports.

To reinforce the lecture and accelerate mastery of the material, each student will complete a challenging test suite for real-world, system-based design.

Objectives
At the end of this workshop the student should be able to:
  • Build a SystemVerilog verification environment
  • Define testbench components using object-oriented programing.
  • Develop a stimulus generator to create constrained random test stimulus
  • Develop device driver routines to drive DUT input with stimulus from generator
  • Develop device monitor routines to sample DUT output
  • Develop self-check routines to verify correctness of DUT output
  • Abstract DUT stimulus as data objects
  • Execute device drivers, monitors and self-checking routines concurrently
  • Communicate among concurrent routines using events, semaphores and mailboxes
  • Develop functional coverage to measure completeness of test
  • Use SystemVerilog Packages

Course Outline

Uunit 1
  • The Device Under Test
  • SystemVerilog Verification Environment
  • SystemVerilog Testbench Language Basics
  • Driving and Sampling DUT Signals
Uunit 2
  • Managing Concurrency in SystemVerilog
  • Object Oriented Programming: Encapsulation
  • Object Oriented Programming: Randomization
Uunit 3
  • Object Oriented Programming: Inheritance
  • Inter-Thread Communications
  • Functional Coverage
  • SystemVerilog UVM preview



第三阶段 Synopsys SystemVerilog VMM培训

SystemVerilog Verification Using VMM Methodology

OVERVIEW

In this hands-on workshop, you will learn how to develop a VMM SystemVerilog test environment structure which can implement a number of different test cases with minimal modification. Within this VMM environment structure, you will develop stimulus factories, check and coverage callbacks, message loggers, transactor managers, and data flow managers. Once the VMM environment has been created, you will learn how to easily add extensions for more test cases.
After completing the course, you should have developed the skills to write a coverage-driven random stimulus based VMM testbench that is robust, re-useable and scaleable.

OBJECTIVES

At the end of the course you should be able to:

Develop an VMM environment class in SystemVerilog
Implement and manage message loggers for printing to terminal or file
Build a random stimulus generation factory
Build and manage stimulus transaction channels
Build and manage stimulus transactors
Implement checkers using VMM callback methods
Implement functional coverage using VMM callback methods

COURSE OUTLINE

Unit 1
SystemVerilog class inheritance review
VMM Environment
Message Service
Data model

Unit 2
Stimulus Generator/Factory
Check & Coverage
Transactor Implementation
Data Flow Control
Scenario Generator
Recommendations

第四阶段 SystemVerilog Verification using UVM

Overview
In this hands-on workshop, you will learn how to develop a UVM 1.1 SystemVerilog testbench environment which enables efficient testcase development. Within this UVM 1.1 environment, you will develop stimulus sequencer, driver, monitor, scoreboard and functional coverage. Once the UVM 1.1 environment has been created, you will learn how to easily manage and modify the environment for individual testcases.

Objectives
At the end of this workshop the student should be able to:
  • Develop UVM 1.1 tests
  • Implement and manage report messages for printing to terminal or file
  • Create random stimulus and sequences
  • Build and manage stimulus sequencers, drivers and monitors
  • Create configurable agents containing sequencer, driver and monitor for re-use
  • Create and manage configurable environments including agents, scoreboards, TLM ports and functional coverage objects
  • Implement a collection of testcases each targeting a corner case of interest
  • Create an abstraction of DUT registers and manage these registers during test, including functional coverage and self-test

Audience Profile
Design or Verification engineers who develop SystemVerilog testbenches using UVM 1.1 base classes.

Prerequisites
To benefit the most from the material presented in this workshop, students should have completed the SystemVerilog Testbench workshop.

Course Outline
Unit 1
  • SystemVerilog OOP Inheritance Review
    • Polymophism
    • Singleton Class
    • Singleton Object
    • Proxy Class
    • Factory Class
  • UVM Overview
    • Key Concepts in UVM: Agent, Environment and Tests
    • Implement UVM Testbenches for Re-Use across Projects
    • Code, Compile and Run UVM Tests
    • Inner Workings of UVM Simulation including Phasing
    • Implement and Manage User Report Messages
  • Modeling Stimulus (Transactions)
    • Transaction Property Implementation Guidelines
    • Transaction Constraint Guidelines
    • Transaction Method Automation Macros
    • User Transactiom Method Customization
    • Implement Tests to Control Transaction Constraints
  • Creating Stimulus Sequences
    • Sequence Execution Protocol
    • Using UVM Macros to create and manage Stimulus
    • Implementing User Sequences
    • Implicitly Execute Sequences Through Configuration in Environment
    • Explicitly Execute Sequences in Test
    • Control Sequences through Configuration
Unit 2
  • Component Configuration and Factory
    • Establish and Query Component Parent-Child Relationships
    • Set Up Component Virtual SystemVerilog Interfaces with uvm_config_db
    • Constructing Components and Transactions with UVM Factory
    • Implement Tests to Configure Components
    • Implement Tests to Override Components with Modified Behavior
  • TLM Communications
    • TLM Push, Pull and Fifo Modes
    • TLM Analysis Ports
    • TLM Pass-Through Ports
    • TLM 2.0 Blocking and Non-Blocking Transport Sockets
    • DVE Waveform Debugging with Recorded UVM Transactions
  • Scoreboard & Coverage
    • Implement scoreboard with UVM In-Order Class Comparator
    • Implement scoreboard UVM Algorithmic Comparator
    • Implement Out-Of-Order Scoreboard
    • Implement Configuration/Stimulus/Correctness Coverage
  • UVM Callback
    • Create User Callback Hooks in Component Methods
    • Implement Error Injection with User Defined Callbacks
    • Implement Component Functional Coverage with User Defined Callbacks
    • Review Default Callbacks in UVM Base Class
Unit 3
  • Virtual Sequence/Sequencer
    • Disable Selected Sequencer in Agents through the Sequencer抯 揹efault? Configuration Field
    • Implement Virtual Sequence and Sequencer to Manager Sequence Execution within Different Agents
    • Implement uvm_event for Synchronization of Execution among Sequences in the Virtual Sequence
    • Implement Grab and Ungrab in Sequences for exclusive access to Sequencer
  • More on Phasing
    • Managing Objections within Component Phases
    • Implement Component Phase Drain Time
    • Implement Component Phase Domain Synchronization
    • Implement User Defined Domain and Phases
    • Implement UVM Phase Jumping
  • Register Layer Abstraction (RAL)
    • DUT Register Configuration Testbench Architecture
    • Develop DUT Register Abstration (.ralf) File
    • Use ralgen Utility to Create UVM Register Model Class Files
    • Create UVM Register Adapter Class
    • Develop and Execute Sequences Using UVM Register Models
    • Use UVM Built-In Register Tests to Verify DUT Register Operation
    • Enable RAL Functional Coverage
  • Summary
    • Review UVM Methodology
    • Review Run-Time Command Line Debug Switche



曙海教育实验设备
fpga培训实验板
fpga培训实验
fpga图像处理
曙海培训实验设备
fpga培训班
 
本课程部分实验室实景
曙海实验室
实验室
曙海培训
 
版权所有:曙海信息网络科技有限公司 copyright 2000-2016
 
上海总部培训基地

地址:上海市云屏路1399号26#新城金郡商务楼310。
(地铁11号线白银路站2号出口旁,云屏路和白银路交叉口)
邮编:201821
热线:021-51875830 32300767
传真:021-32300767
业务手机:15921673576
E-mail:officeoffice@126.com
客服QQ: 849322415
北京培训基地

地址:北京市昌平区沙河南街11号312室
(地铁昌平线沙河站B出口) 邮编:102200 行走路线:请点击这查看
热线:010-51292078
传真:010-51292078
业务手机:15701686205
E-mail:qianru@51qianru.cn
客服QQ:1243285887
深圳培训基地

地址:深圳市环观中路28号82#201室

热线:4008699035
传真:4008699035
业务手机:13699831341

邮编:518001
信箱:qianru2@51qianru.cn
客服QQ:2472106501
南京培训基地

地址:江苏省南京市栖霞区和燕路251号金港大厦B座2201室
(地铁一号线迈皋桥站1号出口旁,近南京火车站)
热线:4008699035
传真:4008699035
邮编:210046
信箱:qianru3@51qianru.cn
客服QQ:1325341129
 
成都培训基地

地址:四川省成都市高新区中和大道一段99号领馆区1号1-3-2903 邮编:610031
热线:4008699035 业务手机:13540421960
客服QQ:1325341129 E-mail:qianru4@51qianru.cn
武汉培训基地

地址:湖北省武汉市江岸区汉江北路34号 九运大厦401室 邮编:430022
热线:4008699035
客服QQ:849322415
E-mail:qianru5@51qianru.cn
广州培训基地

地址:广州市越秀区环市东路486号广粮大厦1202室

热线:4008699035
传真:4008699035

邮编:510075
信箱:qianru6@51qianru.cn
西安培训基地

地址:西安市雁塔区高新二路12号协同大厦901室

热线:029-86699670
业务手机:18392016509
传真:029-86699670
邮编:710054
信箱:qianru7@51qianru.cn
 
沈阳培训基地

地址:辽宁省沈阳市东陵浑南新区沈营路六宅臻品29-11-9 邮编:110179
热线:4008699035
E-mail:qianru8@51qianru.cn
郑州培训基地

地址:郑州市高新区雪松路锦华大厦401

热线:4008699035

邮编:450001
信箱:qianru9@51qianru.cn
石家庄培训基地

地址:石家庄市高新区中山东路618号瑞景大厦1#802

热线:4008699035
业务手机:13933071028
传真:4008699035
邮编:050200
信箱:qianru10@51qianru.cn
 

双休日、节假日及晚上可致电值班电话:021-51875830 值班手机:15921673576


备案号:沪ICP备08026168号

.(2014年7月11)......................................................................