1、培训过程中，如有部分内容理解不透或消化不好，可免费在以后培训班中重听；
        2、培训结束后,培训老师留给学员手机和Email,免费提供半年的技术支持，充分保证培训后出效果；
        3、培训合格学员可享受免费推荐就业机会。 。专注高端培训13年，曙海提供的证书得到本行业的广泛认可，学员的能力得到大家的认同，受到用人单位的广泛赞誉。

培训方式以讲课和实验穿插进行。

IC Compiler 1?

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Overview
The workshop starts out with a high-level introduction to IC Compiler? graphical user interface, during which you will learn about the 3 core commands place_opt, clock_opt, and route_opt, as well as the more targeted atomic commands for more specific needs.

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You will learn the details of design and timing setup, including setting up physical and logical libraries, importing design formats and floorplans, and setting the design up for proper timing analysis.

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The workshop goes in-depth into using IC Compiler to perform placement, power optimization, scan optimization, clock tree synthesis and routing operations, including interleaved logic optimizations. You will also learn how to perform Design-for-Manufacturing tasks in IC Compiler, including antenna fixing, via doubling, metal filling, and critical area optimization. Another unit is dedicated to the topic of the new Multi Scenario capabilities, including how to apply SDC constraint files and operating conditions and how to perform analysis and optimization in parallel. The unit will also show you the advantages of using on-chip-variation mode.

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The class explores the new Design Planning features in IC Compiler, which support full flat floorplanning including automatic macro placement, power network synthesis and analysis, and prototype route and optimization.

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The workshop is accompanied by comprehensive hands-on labs, which provide an opportunity to apply all concepts covered during the lectures.

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Objectives?
At the end of this workshop the student should be able to:?
?? Read necessary files required to run IC Compiler, resolving common errors/warnings?
?? Set up timing for analysis and optimizations?
?? Perform placement and optimizations?
?? Analyze congestion maps and reports?
?? Perform power optimization?
?? Perform scan reordering using ScanDEF?
?? Set up the design for clock tree synthesis?
?? Perform clock tree synthesis and post-CTS optimizations?
?? Analyze timing and clock specifications post CTS?
?? Route the design using the core and atomic commands?
?? Describe the need for Multi-corner, Multi-Mode analysis, and optimization?
?? Specify a scenario in IC Compiler?
?? Analyze the design for SI and perform SI optimizations?
?? Perform unconstrained and freeze silicon ECOs?
?? Perform antenna fixing, via doubling, metal filling, filler cell insertion, critical area optimization?
?? Create a flat floorplan including core and IO area setup, power network synthesis and routing, timing driven macro placement?
?? Perform power network analysis and virtual pad insertion?

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Audience Profile
ASIC, back-end,?or?layout designers with experience in standard-cell-based automatic Place and Route.

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Prerequisites
To benefit the most from the material presented in this workshop, students should have working knowledge of Physical Design using Physical Compiler, Astro,?or?any other physical design tool.

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Course Outline?

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Unit 1?
?? Introduction?
?? IC Compiler Basic Flow?
?? Design Planning?

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Unit 2?
?? Placement, Power and Test?
?? Clock Tree Synthesis?

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Unit 3?
?? Multi Scenario Optimization?
?? Routing and Signal Integrity?
?? Chip Finishing and DFM?