1、培训过程中，如有部分内容理解不透或消化不好，可免费在以后培训班中重听；
        2、培训结束后,培训老师留给学员手机和Email,免费提供半年的技术支持，充分保证培训后出效果；
        3、培训合格学员可享受免费推荐就业机会。 。专注高端培训13年，曙海提供的证书得到本行业的广泛认可，学员的能力得到大家的认同，受到用人单位的广泛赞誉。

培训方式以讲课和实验穿插进行。

阶段一

Overview
In this workshop you will learn to use DFT Compiler to perform RTL and gate-level DFT checks and insert scan using top-down and bottom-up flows. The workshop will show you how to analyze the reported data to identify common DFT violations and then fix the original RTL design.?

The workshop explores essential techniques to support large, multi-million gate SOC designs including the bottom-up scan insertion flow in the logical (Design Compiler) domain. Techniques learned include: performing scan insertion in a top-down flow; meeting scan requirements for number of scan chains, maximum chain length and reusing functional pins for scan testing; and using Adaptive Scan (DFTMAX) to insert additional DFT hardware to reduce the test time and the test data volume required for a given fault coverage.?

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Objectives?
At the end of this workshop the student should be able to:?
Define the test protocol for a design and customize the initialization sequence, if needed?
Perform DFT checks at both the RTL and gate-levels?
State common design constructs that cause typical DFT violations?
Automatically correct certain DFT violations at the gate-level using AutoFix.?
Insert scan to achieve well-balanced top-level scan chains and other scan design requirements?
Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and Place & Route.?
Implement Rapid Scan Synthesis (RSS) in a top-down scan insertion flow achieving well-balanced scan chains?
Modify a bottom-up scan insertion script for full gate-level designs to use Test Models/ILMs with RSS and run it?
Preview top-level chain balance using test models/ILMs after block-level scan insertion and revise block level scan architecture as needed to improve top level scan chain balance.?
Modify a scan insertion script to include DFT-MAX Adaptive Scan compression?
Configure DFT Compiler to support low power flows including clock gating and multivoltage?

Audience Profile
Design and Test engineers who need to check for, identify and fix design-for-test violations in their RTL?or?gate-level designs, insert scan into possibly multi-million gate ASICs, and export design files to ATPG and Place&Route tools.

Prerequisites
There are no prerequisites for this workshop. Prior experience with Design Compiler, Design Vision and writing Synopsys TCL scripts is useful, but not required.

Course Outline?

Unit 1
Introduction to Scan Testing
DFTC User Interfaces
Creating Test Protocols
DFT for Clocks and Resets
meeting scan requirements for number of scan chains, maximum chain length and reusing functional pins for scan testing; inserting an On-Chip Clocking (OCC) controller for At-Speed testing using internal clocks; IEEE 1500 standard; and drive low power pattern requirement through ATPG generations.

Unit 2
DFT for Buses/Tristates
Top-Down Scan Insertion
Exporting Design Files
New Features

Unit 3
High Capacity DFT Flows
DFT MAX
Low Power DFT
Conclusion

阶段二

Unit 1
·????DFT Compiler Flows

·????DFT Compiler Setup

·????Test Protocol

·????DFT Design Rule Checks

Unit 2

·????DFT DRC GUI Debug

·????DRC Fixing

·????Top-Down Scan Insertion

Unit 3

·????Exporting Files

·????High Capacity DFT Flows

·????Multi-Mode DFT

·????DFT MAX

阶段三

unit 1. Understanding Scan Testing
? Define the test protocol for a design

? Perform DFT checks at both the RTL and gate-levels

? State common clocking and reset/set design constructs that cause typical DFT violations

? Automatically fix certain DFT violations at the gate-level using AutoFix

unit 2. DFTC User Interfaces

unit 3. Creating Test Protocols

unit 4. DFT for Clocks and Resets


unit 5. DFT for Tristate Nets
? State design constructs that cause typical DFT violations and how you can workaround these problems:

2　　 Tristate nets?

2　　 Bidirectional pins?

2　　 Embedded memories

? Insert scan to achieve well-balanced top-level scan chains and other scan design requirements

unit 6. DFT for Bidirectional Pins

unit 7. DFT for Embedded Memories

unit 8.Top-Down Scan Insertion

unit 9.Exporting Design Files
? Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and Place & Route?

? Customize the test initialization sequence, if needed?

? Modify a bottom-up scan insertion script for full?
gate-level designs to use Test Models/ILMs with RSS and run it

? Preview top-level chain balance using test models/ILMs after block level scan insertion and revise block level scan architecture as needed to improve top-level scan chain balance

? Insert additional observe test points to reduce number of ATPG patterns

unit 10. High Capacity DFT Flows

unit 11.Test Data Volume Reduction