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            SystemVerilog Testbench培训班
   入学要求

        学员学习本课程应具备下列基础知识:
        ◆ 有数字电路设计和硬件描述语言的基础或自学过相关课程。

   班级规模及环境
       为了保证培训效果,增加互动环节,我们坚持小班授课,每期报名人数限3到5人,多余人员安排到下一期进行。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦
近开课时间(周末班/连续班/晚班)
SystemVerilog Testbench培训班:2024年11月30日......
   学时
     ◆课时: 共5天,30学时

        ◆外地学员:代理安排食宿(需提前预定)
        ☆注重质量
        ☆边讲边练

        ☆合格学员免费推荐工作

        

        专注高端培训17年,曙海提供的课程得到本行业的广泛认可,学员的能力
        得到大家的认同,受到用人单位的广泛赞誉。

        ★实验设备请点击这儿查看★
   新优惠
       ◆团体报名优惠措施:两人95折优惠,三人或三人以上9折优惠 。注意:在读学生凭学生证,即使一个人也优惠500元。
   质量保障

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、培训结束后,培训老师留给学员手机和Email,免费提供半年的技术支持,充分保证培训后出效果;
        3、培训合格学员可享受免费推荐就业机会。 。专注高端培训13年,曙海提供的证书得到本行业的广泛认可,学员的能力得到大家的认同,受到用人单位的广泛赞誉。

             SystemVerilog Testbench培训班

 

Overview
????? In this hands-on workshop, you will learn how to develop a VMM SystemVerilog test environment structure which can implement a number of different test cases with minimal modification. Within this VMM environment structure, you will develop stimulus factories, check and coverage callbacks, message loggers, transactor managers, and data flow managers. Once the VMM environment has been created, you will learn how to easily add extensions for more test cases.
????? After completing the course, you should have developed the skills to write a coverage-driven random stimulus based VMM testbench that is robust, re-useable and scaleable.
Objectives
At the end of this workshop the student should be able to:
  • Develop an VMM environment class in SystemVerilog
  • Implement and manage message loggers for printing to terminal or file
  • Build a random stimulus generation factory
  • Build and manage stimulus transaction channels
  • Build and manage stimulus transactors
  • Implement checkers using VMM callback methods
  • Implement functional coverage using VMM callback methods
Audience Profile
????? Design or Verification engineers who develop SystemVerilog testbenches using VMM base classes
Prerequisites
????? To benefit the most from the material presented in this workshop, students should:
Have taken the SystemVerilog Testbench workshop
OR
  • Generating OpenVera testbench templates
  • Creating/Using OpenVera Virtual Ports
  • Developing testbench components as OOP classes
  • Creating Coverage Group for functional coverage
Course Outline
1
  • SystemVerilog class inheritance review
  • VMM Environment
  • Message Service
  • Data model
2
  • Stimulus Generator/Factory
  • Check & Coverage
  • Transactor Implementation
  • Data Flow Control
  • Scenario Generator
  • Recommendations